This invention relates to a communication system using a spread spectrum system. More particularly, the present invention relates to a spread spectrum receiver by means of a digital matched filter used for synchronous acquisition and retention so as to de-spread those signals which are subjected to spectrum spreading modulation and are then transmitted.
To receive spread spectrum signals correlation reception for synchronizing the spreading codes of the reception signals with the spreading codes used for de-spreading and demodulation must be executed. A correlation reception method can be classified broadly into active correlation and passive correlation. It is well known that in comparison with the active correlation, the passive correlation has the advantage that initial synchronization acquisition can be generally completed within a shorter time. A digital matched filter (hereinafter called the "MF") is one of the means for accomplishing the passive correlation method, and has been put into practical application with the progress of the LSI technologies in recent years.
The matched filter preserves an inputted reception sequence over m taps, and executes multiply-add calculation between the reception data of each tap and the spreading code used for de-spreading within one operation clock period. The number of taps m is set to be equal to a spread factor Gp, and a correlation value for one symbol is determined for each operation clock.
FIG. 1 shows the arrangement of a conventional MF accomplished by digital devices as a prior art example (a part of the arrangement of STEL-3340 manufactured by Stanford Telecom Co., for example). This diagram shows an example in which the reception signal Rx(t) sampled at a rate 4 times a chip rate (over-sample ratio k=4), for example, is de-spread by the MF having the number of taps of 64, for example, in a spread spectrum communication system having a spread factor Gp=64, for example. This MF comprises an input signal sequence register block 24 for recording the reception signals, a coefficient register block 20, a multiplication block 21 for multiplying a reception signal by a spreading code, and an addition block 203 for adding the multiplication results of m taps. The input signal sequence register block 24 comprises 256 stages of reception sequence input delay devices 2400 to 2462. The coefficient register block 20 comprises 64 stages of spreading code coefficient registers 22 (2200 to 2263) and 64 stages of spreading code coefficient delay devices 23 (2300 to 2363). The delay time T of each spreading code coefficient delay device 2300 to 2363 corresponds to the time width of one chip of the spreading code while the delay time D of each reception sequence input delay device 2400 to 2462 corresponds to one operation clock time for sampling the reception signal Rx(t). Since sampling is done at the over-sample ratio of k=4 in this case, the relationship T=4.times.D is established. In the drawing, reference numeral 4D represents that the delay devices having the delay time D are cascaded in four stages. The taps (tap0(t) to tap63(t)) are extended for every four stages of the reception sequence input delay devices 2400 to 2462 so cascaded.
The reception signals Rx(t) are serially inputted to the reception sequence input delay devices 24. Because the delay devices having the delay time D are cascaded in four stages between the adjacent taps, tap0(t), tap1(t), . . . , tap63(t) output the sampled reception signal sequence per chip (time width=T). That is,
tap0(t)=Rx(t-252) PA1 tap1(t)=Rx(t-248) PA1 tap2(t)=Rx(t-244) . . . PA1 tap63(t)=Rx(t)
On the other hand, the spreading code sequence (for example, PN(0), PN(4), PN(8), . . . , PN(252)) is inputted to each of the spreading code coefficient registers 22 (C0, C1, C2, . . . , C63). When the cycle of the spreading code sequence in the spread spectrum communication system is 64 chips, the content of each coefficient register 22 is fixed. However, in order to reduce mutual interference between the codes, it is generally preferred to execute spreading by using a spreading code sequence having a longer spreading code length. When de-spreading of a continuous reception signal sequence is executed by using the spreading code having a spreading code length extending between a plurality of symbols (one symbol=64 chips), the content of each coefficient register 22 is updated in the interval of 64 chips (256 operation clocks). More concretely, each of the spreading code coefficient delay devices 2300 to 2363 of the 64th stage shifts its content to the delay device of the next stage for every chip rate (4 operation clocks). At the point of time at which 256 operation clocks pass by, the spreading code sequence held by each of the spreading code coefficient delay devices 2300 to 2363 of the 64th stage is updated to the spreading code sequence of the next symbol and is altogether read into the corresponding one of the spreading code coefficient registers 2200 to 2263 of the 64th stage when the input of a load timing signal Wc is received.
The output from each tap and the corresponding spreading code sequence are multiplied by the corresponding one of the multipliers 2100 to 2163, each product is added by the addition block 203, and a correlation value Corr(t) is outputted. These processes are expressed by the formula given below. EQU Corr(t)=tap0(t).times.C0+tap1(t).times.C1+ . . . , tap63(t).times.C63
Assuming that the system starts operating at t=0, the correlation value expressed by the following equation can be obtained at t=253 as the de-spreading demodulation result for the first one symbol: EQU Corr(252)=Rx(0).times.PN(0)+Rx(4).times.PN(4)+ . . . , Rx(252).times.PN(252)
When t&gt;252, the correlation values acquired by the de-spreading demodulation process at the timings deviated by one sample clock for each operation clock are serially outputted.
As described above, the spread spectrum receiver executes instantaneously the multiply-add calculation of the reception data of each tap and the spreading code, that is, the de-spreading process, and can therefore execute initial synchronization acquisition at a high speed. Because the output can be obtained by isolating the multi-path components in a transfer path at resolution of the sampling rate, the spread spectrum receiver has the advantage that a path search for RAKE reception can be effectively done.
However, when the MF is materialized by the digital devices, an extremely large number of gates such as the digital delay devices, the multipliers and the adders are necessary as already described, and the problem remains in that the circuit scale is very great. Because the reception signal Rx inputted to the delay device 2462 of the initial stage is shifted serially to the delay devices of the subsequent stages, all the gates constituting the input sequence coefficient delay devices 2400 to 2462, the multipliers 2100 to 2163 and the addition block 203 operate for each clock, and another problem develops in that power consumption is extremely great.
Recently, a cellular mobile communication system (IS-95) employing the spread spectrum has been put into practical application in U.S.A., Hong Kong, Korea, and so forth. In this communication system, the application of the spread spectrum receiver by the MF is expected due to its advantages such as its high speed initial synchronization acquisition, flexibility of the path search for RAKE reception, and so forth. To put the spread spectrum receiver by the MF into practical use as the cellular mobile communication system, lower power consumption, smaller circuit scale and lower cost of production have been strongly required. Nonetheless, the de-spreading block using the MF is not free from the problems of the large circuit scale and large power consumption as described above.
The causes can be broadly divided into the following two. First, the conventional MF needs k stages (k=over-sampling ratio to a chip rate) of input sequence delay devices, one spreading code coefficient register and one multiplier per tap. For this reason, the circuit scale increases substantially proportionally to the number of taps. Second, because the processes from the delaying process of n stages (n=k (over-sampling ratio).times.m (number of taps)) of input sequences to the multiply-add calculation of the input sequence and the spreading code sequence are collectively executed by one clock, a large number of gates operate simultaneously for each clock, and invite the increase of power consumption.